Microsoft + Quantinuum reported (Nature, blog linked below) logical error correction and detection on Quantinuum's trapped-ion hardware with two abelian stabilizer codes, verbatim, "a 12-qubit code encoding two logical qubits and a 16-qubit tesseract color code" and "logical error-rate improvements ranging from 11x to 800x over corresponding physical circuit baselines." Those are their measured figures, on different codes; we do not reproduce them. We are not a hardware competitor, but a companion sandbox that runs an abelian code (Z₂ toric, the surface code's topological order) and our non-abelian Fibonacci string-net (d_τ = φ) on identical machinery under representative trapped-ion noise, to explore a frontier their abelian work doesn't.

The frontier: the road to a universal gate set. The blog's demonstrated circuits (Bell and cat states) are Clifford: they need no magic states, and the blog does not claim any. But any universal fault-tolerant machine built on abelian codes eventually needs the non-Clifford T-gate, which abelian codes supply through magic-state distillation (a general, well-established architectural cost, not something attributed to their specific demo). Fibonacci anyons are braiding-universal: the T-gate comes from braiding, so that distillation overhead is zero (gold card). The honest trade: Fibonacci instead pays an expensive non-abelian decoder. The demo lets you see that trade.

Negative control. The gold and red curves differ only by the F-symbol that makes the code Fibonacci: same lattice, noise, projective syndrome, decoder, and entanglement-fidelity metric. If φ washed, the curves would coincide. So the interesting question is the universality cost, not the logical-error rate.

Where real ion devices sit (green band). The solid green line is each device's sourced gate-error floor (Quantinuum H2 0.156%; IonQ Aria 0.40%, both 2-qubit gate errors); the dashed line adds a schedule-dependent idle-dephasing estimate. With the real, Microsoft-published coherence times (T₂ ≈ 1 s for IonQ Aria, ≈ 10⁶ µs for H2), idle dephasing over a gate is only ~0.02–0.06%, so the band is a hair's width and the operating point is essentially the gate error. Both ion devices sit well below the ~10% code-capacity threshold: trapped ions' long coherence is exactly why they're a clean QEC substrate. (An earlier draft used a 10 ms T₂ that made dephasing look material; Microsoft's published 1 s figure corrects that.)

Honest scope (no overclaiming). This is code-capacity noise at a single distance, not a circuit-level fault-tolerance threshold; the device spec is reduced to an effective per-edge error = gate error + a model-dependent idle-dephasing term (a conservative single-MS-gate window; a fuller syndrome-round schedule would raise it for slow-gate devices). The blue dashed line is the literal SurfaceQEC in its own binary metric (heights not directly comparable). No "we beat Microsoft", just a companion design sandbox. Computed live from phi-quantum-sim-cpp via WebAssembly.

Sources. Microsoft figures (11×–800×, code sizes): Microsoft Quantum blog, on the Nature paper "Improved quantum processor logical error rates via correction and detection" (quoted verbatim). Quantinuum H2 device specs (2q error 0.156%, T₂ ≈ 10⁶ µs): Moses et al., Phys. Rev. X 13, 041052 (2023), Table II. IonQ Aria specs (2q error 0.40% from 99.6% fidelity, T₂ = 1 s, T1 10–100 s, 135 µs / 600 µs gates, SPAM 99.61%): Microsoft Learn: IonQ provider (Azure Quantum), ms.date 2025-09-17 (Microsoft publishes Aria's spec table; Forte's is not on the page). Our H2/Aria are representative noise models for this simulation; the blog does not state which Quantinuum model its result used. All logical-error curves, GSD, edge counts, and the Fibonacci-vs-Z₂ comparison are computed by our own exact code (phi-quantum-sim-cpp / -stringnet-cpp / -mps-cpp).